1. Technical Field
The present invention relates to a semiconductor device having a trench structure and a manufacturing method thereof and, in particular, to a high-frequency switching MOSFET having a trench structure and a manufacturing method thereof.
2. Description of the Prior Art
FIG. 5 is a schematic sectional view showing the structure of a semiconductor device provided with a MOSFET having a conventional trench structure.
Formed on the surface of a silicon substrate 51 is an N− epitaxial layer 52, and formed on the N− epitaxial layer 52 is a diffusion region 65. A plurality of trenches 54 are formed at a uniform interval so as to penetrate through the diffusion region 65 to the middle of the N− epitaxial layer 52 in the thickness direction thereof. A gate electrode 55 made of polysilicon which is made conductive by introduction of an impurity is arranged inside the trench 54.
A gate oxide film 56 is provided along the inner wall of the trench 54. That is, the gate electrode 55 is opposed to the N− epitaxial layer 52 and the diffusion region 65 with the gate oxide film 56 interposed therebetween. The inner side wall of the trench 54 is formed as a substantially flat face and the bottom of the trench 54 constitutes a curved face projected to the silicon substrate 51 side. In a reflection of such a shape of the trench 54, the interface between the gate oxide film 56 and the diffusion region 65 and between the gate oxide film 56 and N− epitaxial layer 52 has a flat face 56f and a curved face 56c. The flat face 56f is formed along a face at the diffusion region 65, which face has a specific plane direction to give a low resistance when electric current flows along the face.
An N+ source region 57 is formed at the periphery (rim) of the trench 54 in a surface layer portion of the diffusion region 65. The rest of the diffusion region 65 constitutes a channel region 53 of a P-conductivity type.
An insulating film 59 made of silicon oxide is formed so as to cover an upper part of the trench 54. The insulating film 59 also exists at the rim of the trench 54 (on the N+ source region 57) in a plan view. A contact hole 60 is formed between two adjacent insulating films 59. An electrode film 61 made of metal such as aluminum is provided on the diffusion region 65 and the insulating film 59. The electrode film 61 is formed so as to fill the contact hole 60.
In operation (ON state) of the above semiconductor device, electric current (drain current) flows across the N+source region 57 and the N− epitaxial layer 52. The drain current flows near the gate oxide film 56 in the channel region 53, along the gate oxide film 56.
Such a semiconductor device is disclosed in, for example, Japanese Unexamined Patent Publication No. 8-167711 (1966).
A semiconductor device constructed as described above, however, cannot be used suitably for high-frequency switching (a DC-DC converter, for example). Although low ON resistance and low switching loss are required for a semiconductor device to be used for such purpose, a semiconductor device constructed as described above cannot strike a balance between reduction of ON resistance and reduction of switching loss. This is for the following reason.
Drain current, which flows near the gate oxide film 56 along the gate oxide film 56, is to flow along the curved face 56c when the current comes near the curved face 56c, in a state where the channel region 53 is in contact with the curved face 56c. Therefore, since the path of the drain current includes a path which deviates from a face having a plane direction to give a low resistance, the ON resistance is increased. Accordingly, in order to decrease the ON resistance, the channel region 53 needs to be in contact only with the flat face 56f of the gate oxide film 56 as shown in FIG. 5. That is, the curved face 56c is made contact with the N− epitaxial layer 52 by the whole area.
This, however, causes increase of the area of an opposed portion of the gate electrode 55 and the N− epitaxial layer 52, increase of the capacity between the N− epitaxial layer 52 and the gate electrode 55, i.e. a drain-gate capacity CDG, and increase of the switching loss.
A semiconductor device constructed as described above has difficulty in operating satisfactorily by a frequency of 1 MHz, though the device can operate and be used by a frequency of 300 kHz, for example.
When forming the bottom of the trench 54 into a flat face and forming the trench 54 to be shallow with respect to the N− epitaxial layer 52, it is possible to decrease the area of an opposed portion of the gate electrode 55 and the N− epitaxial layer 52 and to decrease the drain-gate capacity CDG. It is, however, difficult to form the trench 54 in such a shape and, even if possible, a corner portion is formed between the bottom of the trench 54 and the inner sidewall and, therefore, favorable characteristics cannot be provided due to concentration of an electric field on this corner portion.